1. Field of the Invention
The present invention relates to a delay locked loop (DLL) circuit and its control method.
2. Description of the Prior Art
FIG. 12 shows an example of a configuration of a conventional DLL circuit. The conventional DLL circuit includes a delay circuit 51, a driver 52, a phase comparator 53, a delay control circuit 54 and a dummy delay circuit 55. In FIG. 12, the phase comparator 53 compares a phase of an input clock INTCLK with a phase of a feedback clock RTNCLK which has passed through the delay circuit 51 and the dummy delay circuit 55 and outputs its comparison signal CNT to the delay control circuit 54. In response to the comparison signal CNT, the delay control circuit 54 adjusts delay time of the delay circuit 51. As shown in FIG. 13, the conventional DLL circuit of FIG. 12 performs a function of keeping a phase difference D between the input clock INTCLK and an output clock DLLCLK constant by the above described feedback circuit.
Operational examples of the phase comparator 53 of the conventional DLL circuit of FIG. 12 are shown in FIGS. 14A and 14B, respectively. In case a reference clock signal REF is low at a rise edge of a clock signal CLK as shown in FIG. 14A, the comparison signal CNT is set to low state. On the other hand, in case the reference clock signal REF is high at the rise edge of the clock signal CLK as shown in FIG. 14B, the comparison signal CNT is set to high state. Timing for switching low state and high state of the comparison signal CNT is determined by the rise edges of the clock signal CLK. The delay time of the delay circuit 51 is increased or reduced by the comparison signal CNT.
A configuration of the delay control circuit 54 of the conventional DLL circuit of FIG. 12 is shown in FIG. 15. The delay control circuit 54 includes a filter circuit 61 and a counter 62. Initially, the comparison signal CNT from the phase comparator 53 is inputted to the filter circuit 61, Only when the comparison signal CNT is kept constant for not less than a predetermined period, the filter circuit 61 generates signals PUP and PDN for commanding increase and decrease of actual delay time, respectively. This is because in case the phase difference is converged to a target value in the phase comparator 53, it is supposed that the comparison signal CNT frequently changes between high state and low state. In this case, since it is not necessary to change the delay time expressly, the delay time is not changed unless the comparison signal CNT is kept constant for not less than the predetermined period.
The counter 62 performs count operation in response to the signals PUP and PDN and outputs, for example, an address signal ADD<7:0> having an 8-bit width from an address “7” to an address “0”. Namely, when the signal PUP is high, the address signal ADD<7:0> increases. On the contrary, when the signal PDN is high, the address signal ADD<7:0>decreases. Finally, the address signal ADD<7:0> is outputted from the counter 62 to the delay circuit 51. The address signal ADD<7:0> inputted to the delay circuit 51 is decoded and is used for changeover of a switch for determining whether or not an actual delay step is used.
FIG. 16 is a timing chart explanatory of operation of the delay control circuit 54 of the conventional DLL circuit. In timing in a leftward portion of FIG. 16, since the comparison signal CNT frequently changes between high state and low state, the signals PUP and PDN are not outputted. Namely, the signals PUP and PDN are set to low state. Then, in timing in a middle portion of FIG. 16, since the comparison signal CNT is continuously held in high state, for example, for not less than twice a period of the input clock INTCLK, the signal PUP is outputted. Namely, the signal PUP is set to high state and the signal PDN is set to low state. Furthermore, in timing in a rightward portion of FIG. 16, since the comparison signal CNT is continuously held in low state, for example, for not less than twice the period of the input clock INTCLK, the signal PDN is outputted. Namely, the signal PUP is set to low state and the signal PDN is set to high state.
In the above described conventional DLL circuit, such a disadvantage is incurred that although the delay time of the delay circuit 51 is a preset default value in an initial state at the time of turning on of a power source and changes from the default value so as to be shortly converged to a desired delay time, i.e., “locked”, a long time is required for locking the delay time. Thus, in, for example, a double data rate synchronous DRAM (DDRSDRAM), since such a product specification that locking of a delay time should be completed within 200 cycles from an initial state is provided, various configurations of the DDRSDRAM are proposed.